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? semiconductor components industries, llc, 2002 june, 2002 rev. 1 1 publication order number: nbsg53a/d nbsg53a 2.5v/3.3vsige selectable differential clock and data d flip-flop/clock divider with reset and ols* the nbsg53a is a multifunction differential d flipflop (dff) or fixed divide by 2 (div/2) clock generator. this is part of the gigacomm ? family of high performance silicon germanium products. a strappable control pin is provided to select between the two functions. the device is housed in a low profile 4x4 mm 16pin flipchip bga (fcbga) package. the nbsg53a is a device with data, clock, ols, reset, and select inputs. differential inputs incorporate internal 50 termination resistors and accept necl (negative ecl), pecl (positive ecl), cmos, cml, or lvds. the ols input is used to program the peaktopeak output amplitude between 0 and 800 mv in five discrete steps. the reset and select inputs are singleended and can be driven with either lvecl or lvcmos input levels. data is transferred to the outputs on the positive edge of the clock. the differential clock inputs of the nbsg53a allow the device to also be used as a negative edge triggered device. ? maximum input clock frequency (dff) > 8 ghz typical (see figures 3, 5, 7, 9, and 10) ? maximum input clock frequency (div/2) > 10 ghz typical (see figures 4, 6, 8, 9, and 10) ? 210 ps typical propagation delay (ols = float) ? 45 ps typical rise and fall times (ols = float) ? div/2 mode (active with select low) ? dff mode (active with select high) ? selectable swing pecl output with operating range: v cc = 2.375 v to 3.465 v with v ee = 0 v ? selectable swing necl output with necl inputs with operating range: v cc = 0 v with v ee = 2.375 v to 3.465 v ? output level select (0 v, 200 mv, 400 mv, 600 mv, or 800 mv peaktopeak output) ? 50 internal input termination resistors on all differential inputs *output level select l = wafer lot y = year w = work week **for further details, refer to application note and8002/d fcbga16 ba suffix case 489 marking diagram** sg 53a lyw device package shipping ordering information nbsg53aba 4x4 mm fcbga16 100 units/tray nbsg53abar2 4x4 mm fcbga16 500/tape & reel board description sg53abaevb nbsg53aba evaluation board http://onsemi.com
nbsg53a http://onsemi.com 2 vtd clk clk vtclk v cc r vtclk d d vtd v cc v ee sel ols q q a b c d 12 34 pin description pin d, d q, q data outputs function data inputs r*, sel* lvecl, lvcmos control inputs (reset, select) v cc positive supply v ee negative supply vtd, vtd , vtclk, vtclk 50 internal input termination resistor clk, clk clock inputs ols (output level select) input * pin will default low when left open. figure 1. pinout (top view) output level select (ols) ols v cc v cc 0.4 v 200 mv q/q vpp 800 mv float 600 mv v cc 0.8 v 600 mv v cc 1.2 v 0 v ee * 400 mv * when an output level of 400 mv is desired and v cc v ee > 3.0 v, 2.0 k resistor should be connected from ols to v ee . ols 150 mv ols sensitivity ols 75 mv n/a ols 100 mv ols 75 mv ols + 100 mv
nbsg53a http://onsemi.com 3 figure 2. simplified logic diagram (a3) d (a2) d (d3) sel (b1) clk (c1) clk (a4) vtd v cc (b3,d1) q (b4) q (c4) flipflop (div/2) flipflop (dff) r d d (a1) vtd (d4) ols r q q v ee (c3) (b2) vtclk (c2) vtclk (d2) r 75 k 75 k 50 50 50 50 0 1 2 2 2 2 2 2 2 truth table r sel d clk q function h x x x l reset l h l z l dff l h h z h dff l l x z q div/2 z = low to high transition interfacing options interfacing options connections cml connect vtclk, vtd and vtclk , vtd to v cc lvds connect vtclk, vtd and vtclk , vtd together accoupled bias vtclk, vtd and vtclk , vtd inputs within common mode range (v ihcmr ) rsecl, pecl, necl standard ecl termination techniques lvttl, lvcmos an external voltage (v thr ) should be applied to the unused differential input. nominal v thr is 1.5 v for lvttl and v cc /2 for lvcmos inputs. this voltage must be within the v thr specification.
nbsg53a http://onsemi.com 4 attributes characteristics value positive operating voltage range for v cc (v ee = 0 v) 2.375 v to 3.465 v negative operating voltage range for v ee (v cc = 0 v) 2.375 v to 3.465 v internal input pulldown resistor (r, sel) 75 k esd protection human body model machine model charged device model > 1.5 kv > 50 v > 4 kv moisture sensitivity (note 1) level 3 flammability rating ul 94 v0 @ 0.125 in oxygen index 28 to 34 transistor count 482 meets or exceeds jedec spec eia/jesd78 ic latchup test 1. for additional information, refer to application note and8003/d. maximum ratings (note 2) symbol parameter condition 1 condition 2 rating units v cc positive power supply v ee = 0 v 3.6 v v ee negative power supply v cc = 0 v 3.6 v v i positive input negative input v ee = 0 v v cc = 0 v v i v cc v i v ee 3.6 3.6 v v v inpp (inin) differential input voltage v cc v ee 2.8 v v cc v ee < 2.8 v 2.8 |v cc v ee | v v i in input current through r t (50 resistor) static surge 45 80 ma ma i out output current continuous surge 25 50 ma ma t a operating temperature range 40 to +70 c t stg storage temperature range 65 to +150 c ja thermal resistance (junctiontoambient) (note 3) 0 lfpm 500 lfpm 16 fcbga 16 fcbga 108 86 c/w c/w jc thermal resistance (junctiontocase) 2s2p (note 3) 16 fcbga 5 c/w t sol wave solder < 15 seconds 225 c 2. maximum ratings are those values beyond which device damage may occur. 3. jedec standard 516, multilayer board 2s2p (2 signal, 2 power).
nbsg53a http://onsemi.com 5 dc characteristics, input with pecl output v cc = 2.5 v; v ee = 0 v (note 4) 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 33 45 57 33 45 57 33 45 57 ma v oh output high voltage (note 5) 1460 1510 1560 1490 1540 1590 1515 1565 1615 mv v ol output low voltage (note 5) (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) (ols = v cc 1.2 v) (ols = v ee ) 555 1235 775 1455 1005 705 1295 895 1505 1095 855 1355 1015 1555 1185 595 1270 810 1490 1040 745 1330 930 1540 1130 895 1390 1050 1590 1220 625 1295 840 1510 1065 775 1355 960 1560 1155 925 1415 1080 1610 1245 mv v outpp output pp voltage (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) (ols = v cc 1.2 v) (ols = v ee ) 715 125 525 0 325 805 215 615 5 415 705 120 520 0 320 795 210 610 0 410 700 120 515 0 320 790 210 605 5 410 mv v ih input high voltage (singleended) (notes 7 and 9) clk, clk , d, d v ee + 1275 v cc 1000* v cc v ee + 1275 v cc 1000* v cc v ee + 1275 v cc 1000* v cc mv v il input low voltage (singleended) (notes 8 and 9) clk, clk , d, d v ee v cc 1400* v ih 150 v ee v cc 1400* v ih 150 v ee v cc 1400* v ih 150 mv v ih input high voltage (singleended) r, sel 1290 1615 1355 1680 1415 1740 mv v il input low voltage (singleended) r, sel 565 890 630 955 690 1015 mv v thr input threshold voltage (singleended) (note 9) v ee + 1125 v cc 75 v ee + 1125 v cc 75 v ee + 1125 v cc 75 mv v ihcmr input high voltage common mode range (differential) (note 6) 1.2 2.5 1.2 2.5 1.2 2.5 v r t internal termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@v ih ) r, sel clk, clk , d, d 35 5 100 50 35 5 100 50 35 5 100 50 a i il input low current (@v il ) r, sel clk, clk , d, d 20 5 100 50 20 5 100 50 20 5 100 50 a note: gigacomm circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been established. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintaine d. 4. input and output parameters vary 1:1 with v cc . v ee can vary +0.125 v to 0.965 v. 5. all outputs loaded with 50 to v cc 2.0 volts. 6. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the dif ferential input signal. 7. v ih cannot exceed v cc . |v ih v thr | < 2600 mv. 8. v il always v ee . |v il v thr | < 2600 mv. 9. v thr is the voltage applied to one input when running in singleended mode. *typicals used for testing purposes.
nbsg53a http://onsemi.com 6 dc characteristics, input with pecl output v cc = 3.3 v; v ee = 0 v (note 10) 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 35 47 59 35 47 59 35 47 59 ma v oh output high voltage (note 11) 2260 2310 2360 2290 2340 2390 2315 2365 2415 mv v ol output low voltage (note 11) (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) (ols = v cc 1.2 v) **(ols = v ee ) 1320 2030 1550 2260 1785 1470 2090 1670 2310 1875 1620 2150 1790 2360 1965 1360 2065 1585 2290 1820 1510 2125 1705 2340 1910 1660 2185 1825 2390 2000 1390 2090 1615 2315 1850 1540 2150 1735 2365 1940 1690 2210 1855 2415 2030 mv v outpp output pp voltage (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) (ols = v cc 1.2 v) **(ols = v ee ) 750 130 550 0 345 840 220 640 0 435 740 125 545 0 340 830 215 635 0 430 735 125 540 0 335 825 215 630 0 425 mv v ih input high voltage (singleended) (notes 13 and 15) clk, clk , d, d v ee + 1275 v cc 1000* v cc v ee + 1275 v cc 1000* v cc v ee + 1275 v cc 1000* v cc mv v il input low voltage (singleended) (notes 14 and 15) clk, clk , d, d v ih 2600 v cc 1400* v ih 150 v ih 2600 v cc 1400* v ih 150 v ih 2600 v cc 1400* v ih 150 mv v ih input high voltage (singleended) r, sel 2090 2415 2155 2480 2215 2540 mv v il input low voltage (singleended) r, sel 1365 1690 1430 1755 1490 1815 mv v thr input threshold voltage (singleended) (note 15) v ee + 1125 v cc 75 v ee + 1125 v cc 75 v ee + 1125 v cc 75 mv v ihcmr input high voltage common mode range (differential) (note 12) 1.2 3.3 1.2 3.3 1.2 3.3 v r t internal termination resistor 45 50 55 45 50 55 45 50 55 i ih input high current (@v ih ) r, sel clk, clk , d, d 35 5 100 50 35 5 100 50 35 5 100 50 a i il input low current (@v il ) r, sel clk, clk , d, d 20 5 100 50 20 5 100 50 20 5 100 50 a note: gigacomm circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been e stab- lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintaine d. 10. input and output parameters vary 1:1 with v cc . v ee can vary +0.925 v to 0.165 v. 11. all outputs loaded with 50 to v cc 2.0 volts. 12. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. 13. v ih cannot exceed v cc . |v ih v thr | < 2600 mv. 14. v il always v ee . |v il v thr | < 2600 mv. 15. v thr is the voltage applied to one input when running in singleended mode. *typicals used for testing purposes. **when an output level of 400 mv is desired an v cc v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee .
nbsg53a http://onsemi.com 7 dc characteristics, necl input with necl output v cc = 0 v; v ee = 3.465 v to 2.375 v (note 16) 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit i ee power supply current 35 47 59 35 47 59 35 47 59 ma v oh output high voltage (note 17) 1040 990 940 1010 960 910 985 935 885 mv v ol output low voltage (note 17) 3.465 v v ee 3.0 v (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) (ols = v cc 1.2 v) **(ols = v ee ) 3.0 v < v ee 2.375 v (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) (ols = v cc 1.2 v) (ols = v ee ) 1980 1270 1750 1040 1515 1945 1265 1725 1045 1495 1830 1210 1630 990 1425 1795 1205 1605 995 1405 1680 1150 1510 940 1335 1645 1145 1485 945 1315 1940 1235 1715 1010 1480 1905 1230 1690 1010 1460 1790 1175 1595 960 1390 1755 1170 1570 960 1370 1640 1115 1475 910 1300 1605 1110 1450 910 1280 1910 1210 1685 985 1450 1875 1205 1660 990 1435 1760 1150 1565 935 1360 1725 1145 1540 940 1345 1610 1090 1445 885 1270 1575 1085 1420 890 1255 mv v outpp output pp voltage 3.465 v v ee 3.0 v (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) (ols = v cc 1.2 v) **(ols = v ee ) 3.0 v < v ee 2.375 v (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) (ols = v cc 1.2 v) (ols = v ee ) 750 130 550 0 345 715 125 525 0 325 840 220 640 0 435 805 215 615 5 415 740 125 545 0 340 705 120 520 0 320 830 215 635 0 430 795 210 610 0 410 735 125 540 0 335 700 120 515 0 320 825 215 630 0 425 790 210 605 5 410 mv v ih input high voltage (singleended) (notes 19 and 21) clk, clk , d, d v ee + 1275 v cc 1000* v cc v ee + 1275 v cc 1000* v cc v ee + 1275 v cc 1000* v cc mv v il input low voltage (singleended) (notes 20 and 21) clk, clk , d, d v ih 2600 v cc 1400* v ih 150 v ih 2600 v cc 1400* v ih 150 v ih 2600 v cc 1400* v ih 150 mv v ih input high voltage (singleended) r, sel 1210 885 1145 820 1085 760 mv v il input low voltage (singleended) r, sel 1935 1610 1870 1545 1810 1485 mv v thr input threshold voltage (singleended) (note 21) v ee + 1125 v cc 75 v ee + 1125 v cc 75 v ee + 1125 v cc 75 mv v ihcmr input high voltage common mode range (differential) (note 18) v ee + 1.2 0.0 v ee + 1.2 0.0 v ee + 1.2 0.0 v i ih input high current (@v ih ) r, sel clk, clk , d, d 35 5 100 50 35 5 100 50 35 5 100 50 a note: gigacomm circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been e stab- lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintaine d. 16. input and output parameters vary 1:1 with v cc . 17. all outputs loaded with 50 to v cc 2.0 volts. 18. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. 19. v ih cannot exceed v cc . |v ih v thr | < 2600 mv. 20. v il always v ee . |v il v thr | < 2600 mv. 21. v thr is the voltage applied to one input when running in singleended mode. *typicals used for testing purposes. **when an output level of 400 mv is desired an v cc v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee .
nbsg53a http://onsemi.com 8 dc characteristics, necl input with necl output v cc = 0 v; v ee = 3.465 v to 2.375 v (note 16) symbol unit 70 c 25 c 40 c characteristic symbol unit max typ min max typ min max typ min characteristic i il input low current (@v il ) r, sel clk, clk , d, d 20 5 100 50 20 5 100 50 20 5 100 50 a i ols ols input current (see figure 11) (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) (ols = v cc 1.2 v) 3.465 v v ee 3.0 v *(ols = v ee ) 3.0 v < v ee 2.375 v (ols = v ee ) 300 1500 1000 300 100 5 100 600 400 900 300 100 300 1500 1000 300 100 5 100 600 400 900 300 100 300 1500 1000 300 100 5 100 600 400 900 300 100 a note: gigacomm circuits are designed to meet the dc specifications shown in the above table after thermal equilibrium has been e stab- lished. the circuit is in a test socket or mounted on a printed circuit board and transverse airflow greater than 500 lfpm is maintaine d. 16. input and output parameters vary 1:1 with v cc . 17. all outputs loaded with 50 to v cc 2.0 volts. 18. v ihcmr min varies 1:1 with v ee , v ihcmr max varies 1:1 with v cc . the v ihcmr range is referenced to the most positive side of the differential input signal. 19. v ih cannot exceed v cc . |v ih v thr | < 2600 mv. 20. v il always v ee . |v il v thr | < 2600 mv. 21. v thr is the voltage applied to one input when running in singleended mode. *typicals used for testing purposes. **when an output level of 400 mv is desired an v cc v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee .
nbsg53a http://onsemi.com 9 ac characteristics v cc = 0 v; v ee = 3.465 v to 2.375 v or v cc = 2.375 v to 3.465 v; v ee = 0 v 40 c 25 c 70 c symbol characteristic min typ max min typ max min typ max unit f max maximum frequency (see figures 3, 5, 7, 9, and 10) dff (see figures 4, 6, 8, 9, and 10) (note 22) div/2 > 8 > 10 > 8 > 10 > 8 > 10 ghz t plh , t phl propagation delay to output differential clk q, q (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) **(ols = v ee ) 160 150 155 155 210 200 205 205 260 250 255 255 160 155 160 160 215 205 210 210 270 255 260 260 165 160 160 160 220 210 215 215 275 260 270 270 ps sel q, q (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) **(ols = v ee ) 165 160 160 160 220 210 215 210 275 260 270 260 170 160 165 160 225 210 220 215 280 260 275 270 170 160 165 165 225 210 220 220 280 260 275 275 r q, q (ols = v cc ) div/2 (ols = v cc ) dff (ols = v cc 0.4 v) div/2 (ols = v cc 0.4 v) dff (ols = v cc 0.8 v, ols = float) div/2 (ols = v cc 0.8 v, ols = float) dff **(ols = v ee ) div/2 **(ols = v ee ) dff 220 200 215 195 220 200 215 195 295 270 285 260 290 265 285 260 370 340 355 325 360 330 355 325 225 205 220 200 220 200 220 200 300 275 290 265 295 270 290 265 375 345 360 330 370 340 360 330 225 205 220 200 220 200 220 200 300 275 290 265 295 270 290 265 375 345 360 330 370 340 360 330 t skew duty cycle skew (notes 23 and 25) dff 5 20 5 20 5 20 ps t jitter output random jitter (rms) dff (see figures 3 and 5) (note 22) 0.5 < 1.5 0.5 < 1.5 0.5 < 1.5 ps v inpp input voltage swing/sensitivity (differential) (note 24) 75 2600 75 2600 75 2600 mv t r t f output rise/fall times (20% 80%) q, q (ols = v cc ) (ols = v cc 0.4 v) (ols = v cc 0.8 v, ols = float) **(ols = v ee ) 30 20 25 25 50 40 45 45 65 60 65 65 30 20 25 25 50 40 45 45 65 60 65 65 30 20 25 25 50 40 45 45 65 60 65 65 ps t s setup time d clk 30 14 30 10 30 13 ps t h hold time d clk 25 12 25 7 25 9 ps t rr reset recovery dff, div/2 40 9 40 12 40 10 ps 22. measured using a 500 mv source, 50% duty cycle clock source. repetitive 1010 input data pattern. all outputs loaded with 50 to v cc 2.0 v. 23. see figure 13. t skew = |t plh t phl | for a nominal 50% differential clock input waveform. 24. v inpp (max) cannot exceed v cc v ee (applicable only when v cc v ee < 2600 mv). 25. see figure 9. duty cycle % vs. frequency. **when an output level of 400 mv is desired an v cc v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee .
nbsg53a http://onsemi.com 10 figure 3. v out /jitter vs. frequency for dff mode (v cc v ee = 3.3 v @ 25 c; repetitive 1010 input data pattern) rms jitter frequency (ghz) v outpp (mv) jitter out ps (rms) 0 100 200 300 400 500 600 700 800 900 123456789101112 0 1 2 3 4 5 6 7 8 9 ols = v cc 0 ols = v cc 0.4 v *ols = v ee ols = v cc 0.8 v, ols = float frequency (ghz) v outpp (mv) 0 100 200 300 400 500 600 700 800 900 123456789101112 ols = v cc 0 ols = v cc 0.4 v *ols = v ee ols = v cc 0.8 v, ols = float figure 4. v out vs. frequency for div/2 mode (v cc v ee = 3.3 v @ 25 c) *when an output level of 400 mv is desired an v cc v ee > 3.0 v, a 2 k resistor should be connected from ols to v ee .
nbsg53a http://onsemi.com 11 figure 5. v out /jitter vs. frequency for dff mode (v cc v ee = 2.5 v @ 25 c; repetitive 1010 input data pattern) rms jitter frequency (ghz) v outpp (mv) jitter out ps (rms) 0 100 200 300 400 500 600 700 800 900 123456789101112 0 1 2 3 4 5 6 7 8 9 ols = v cc 0 ols = v cc 0.4 v ols = v ee ols = v cc 0.8 v, ols = float frequency (ghz) v outpp (mv) 0 100 200 300 400 500 600 700 800 900 123456789101112 ols = v cc 0 ols = v cc 0.4 v ols = v ee ols = v cc 0.8 v, ols = float figure 6. v out vs. frequency for div/2 mode (v cc v ee = 2.5 v @ 25 c)
nbsg53a http://onsemi.com 12 frequency (ghz) v oh /v ol (mv) 0 100 200 300 400 500 600 700 800 900 123456789101112 0 v oh (q) v oh (q ) v ol (q ) v ol (q) 1000 1100 1200 frequency (ghz) v oh /v ol (mv) 0 100 200 300 400 500 600 700 800 900 123456789101112 0 v oh (q) v oh (q ) v ol (q) v ol (q ) 1000 1100 1200 figure 7. v oh /v ol (q/q ) vs. frequency for dff mode (v cc v ee = 3.3 v @ 25 c and ols = v cc 0.8 v, ols = float) figure 8. v oh /v ol (q/q ) vs. frequency for div/2 mode (v cc v ee = 3.3 v @ 25 c and ols = v cc 0.8 v, ols = float)
nbsg53a http://onsemi.com 13 70 0 10 20 30 40 50 60 80 90 100 01 3456789101112 2 frequency (ghz) duty cycle (%) dff mode div/2 mode 70 0 10 20 30 40 50 60 80 90 100 0 1 3456789101112 2 frequency (ghz) duty cycle (%) dff mode div/2 mode figure 9. duty cycle % vs. frequency (v cc v ee = 3.3 v @ 25 c) figure 10. duty cycle % vs. frequency (v cc v ee = 2.5 v @ 70 c)
nbsg53a http://onsemi.com 14 i ols ( a) 700 600 500 400 300 200 100 0 100 200 300 figure 11. typical ols input current vs. ols input voltage (v cc v ee = 3.3 v @ 25 c) v ols (mv) v outpp (mv) 0 200 400 600 800 1000 ols (mv) figure 12. ols operating area v ee v cc v cc 400 v cc 800 v cc 1200 v ee v cc v cc 400 v cc 800 v cc 1200 v cc 75 v cc 250 v cc 550 v cc 700 v cc 900 v cc 1125 v cc 1275 v ee + 100
nbsg53a http://onsemi.com 15 figure 13. ac reference measurement clk clk q q t phl t plh v pp v tt = v cc 2.0 v driver device receiver device qd 50 50 v tt figure 14. typical termination for output driver and device evaluation (refer to application note and8020 termination of ecl logic devices) q d
nbsg53a http://onsemi.com 16 package dimensions fcbga16 ba suffix plastic 4 x 4 (mm) bga flip chip package case 48901 issue o 0.20 laser mark for pin 1 identification in this area d e m a1 a2 a 0.10 z 0.15 z rotated 90 clockwise detail k 5 view mm e 3 x s m x 0.15 y z 0.08 z 3 b 16 x feducial for pin a1 identification in this area 4321 a b c d 4 16 x notes: 1. dimensions are in millimeters. 2. interpret dimensions and tolerances per asme y14.5m, 1994. 3. dimension b is measured at the maximum solder ball diameter, parallel to datum plane z. 4. datum z (seating plane) is defined by the spherical crowns of the solder balls. 5. parallelism measurement shall exclude any effect of mark on top surface of package. dim min max millimeters a 1.40 max a1 0.25 0.35 a2 1.20 ref b 0.30 0.50 d 4.00 bsc e 4.00 bsc e 1.00 bsc s 0.50 bsc k x y m m z on semiconductor is a trademark and is a registered trademark of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circui t, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may b e provided in scillc data sheets and/or specifications can and do vary in dif ferent applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its paten t rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indem nify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and re asonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized u se, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employ er. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. nbsg53a/d gigacomm is a trademark of semiconductor components industries, llc (scillc). literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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